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9-107 9-107 features ? full duplex transmission over a single twisted pair ? selectable 80 or 160 kbit/s line rate ? adaptive echo cancellation ? up to 3km (8971b) and 4 km (8972b) ? isdn compatible (2b+d) data format ? transparent modem capability ? frame synchronization and clock extraction ? mitel st-bus compatible ? low power (typically 50 mw), single 5v supply applications ? digital subscriber lines ? high speed data transmission over twisted wires ? digital pabx line cards and telephone sets ? 80 or 160 kbit/s single chip modem figure 1 - functional block diagram dsti/di cdsti/ f0 /cld c4 /tck f0o /rck ms0 ms1 ms2 regc dsto/do cdsto/ cdo transmit interface prescrambler scrambler control register transmit/ clock receive timing & control status transmit timing master clock phase locked sync detect receive dpll receive interface de - prescrambler descrambler differentially encoded biphase receiver differentially encoded biphase transmitter transmit filter & line driver receive filter -1 +2 mux address echo canceller error signal echo estimate v bias v dd v ss v bias v ref l out l out dis precan l in osc2 osc1 + ? cdi issue 7 may 1995 description the MT8971B (dsic) and mt8972b (dnic) are multi-function devices capable of providing high speed, full duplex digital transmission up to 160 kbit/s over a twisted wire pair. they use adaptive echo-cancelling techniques and transfer data in (2b+d) format compatible to the isdn basic rate. several modes of operation allow an easy interface to digital telecommunication networks including use as a high speed limited distance modem with data rates up to 160 kbit/s. both devices function identically but with the dsic having a shorter maximum loop reach specification. the generic "dnic" will be used to reference both devices unless otherwise noted. the MT8971B/72b is fabricated in mitels iso 2 - cmos process. ordering information MT8971Be 22 pin plastic dip mt8972be 22 pin plastic dip mt8972bc 22 pin ceramic dip MT8971Bp 28 pin plcc mt8972bp 28 pin plcc -40c to + 85c MT8971B/72b digital subscriber interface circuit digital network interface circuit iso 2 -cmos st-bus ? family
MT8971B/72b 9-108 figure 2 - pin connections pin description pin # name description dip plcc 12 l out line out. transmit signal output (analog). referenced to v bias . 23 v bias internal bias voltage output. connect via 0.33 f decoupling capacitor to v dd . 34 v ref internal reference voltage output. connect via 0.33 f decoupling capacitor to v dd . 4,5, 6 5,7, 8 ms2-ms0 mode select inputs (digital). the logic levels present on these pins select the various operating modes for a particular application. see table 1 for the operating modes. 7 9 regc regulator control output (digital). a 512 khz clock used for switch mode power supplies. unused in mas/mod mode and should be left open circuit. 810 f0 /cld frame pulse/c-channel load (digital). in dn mode a 244 ns wide negative pulse input for the master indicating the start of the active channel times of the device. output for the slave indicating the start of the active channel times of the device. output in mod mode providing a pulse indicating the start of the c-channel. 9 12 cdsti/ cdi control/data st-bus in/control/data in (digital). a 2.048 mbit/s serial control & signalling input in dn mode. in mod mode this is a continuous bit stream at the bit rate selected. 10 13 cdsto/ cdo control/data st-bus out/control/data out (digital). a 2.048 mbit/s serial control & signalling output in dn mode. in mod mode this is a continuous bit stream at the bit rate selected. 11 14 v ss negative power supply (0v). 12 15 dsto/do data st-bus out/data out (digital). a 2.048 mbit/s serial pcm/data output in dn mode. in mod mode this is a continuous bit stream at the bit rate selected. 13 16 dsti/di data st-bus in/data in (digital). a 2.048 mbit/s serial pcm/data input in dn mode. in mod mode this is a continuous bit stream at the bit rate selected. 14 17 f0o /rck frame pulse out/receive bit rate clock output (digital). in dn mode a 244 ns wide negative pulse indicating the end of the active channel times of the device to allow daisy chaining. in mod mode provides the receive bit rate clock to the system. 15 19 c4 /tck data clock/transmit baud rate clock (digital). a 4.096 mhz ttl compatible clock input for the master and output for the slave in dn mode. for mod mode this pin provides the transmit bit rate clock to the system. 16 21 osc2 oscillator output . cmos output. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 22 21 20 19 18 17 16 15 22 pin pdip/cerdip lout vbias vref ms2 ms1 ms0 regc f0 /cld cdsti/cdi cdsto/cdo vss vdd lin test lout dis precan osc1 osc2 c4 /tck f0o /rck dsti/di dsto/do 28 pin plcc 27 4 3 2 1 28 26 5 6 7 8 9 10 11 25 24 23 22 21 20 19 17 12 13 14 15 16 18 lout vbias vref nc vdd lin test nc lout dis precan osc1 osc2 nc c4 /tck ms2 nc ms1 ms0 regc f0 /cld nc cdsti/cdi cdsto/cdo vss dsto/do nc f0o /rck dsti/di
MT8971B/72b 9-109 figure 3 - dv port - 80 kbit/s (modes 2, 3, 6) figure 4 - dv port - 160 kbit/s (modes 2, 3, 6) 17 22 osc1 oscillator input . cmos input. d.c. couple signals to this pin. refer to d.c. electrical characteristics for osc1 input requirements. 18 23 precan precanceller disable. when held to logic 1 , the internal path from l out to the precanceller is forced to v bias thus bypassing the precanceller section. when logic 0, the l out to the precanceller path is enabled and functions normally. an internal pulldown (50 k w ) is provided on this pin. 1,6, 11, 18, 20, 25 nc no connection. leave open circuit. 19 24 l out dis l out disable. when held to logic 1, l out is disabled (i.e., output = v bias ). when logic 0, l out functions normally. an internal pulldown (50 k w ) is provided on this pin. 20 26 test test pin. connect to v ss for normal operation. 21 27 l in receive signal input (analog). 22 28 v dd positive power supply (+5v) input. pin description (continued) pin # name description dip plcc aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aaa a aaa a aaa a aaa a aaa aaaa a a a a a a a aaaa aaaa aa aa aa aa aa aa aa aa aa aaaa aaaa a a a a a a a a a a aaa a aaa a aaa a aaa a aaa aaaa a a a a a a aaaaa a a a a a a a aaaa aaaa a a aa aa aa aa aa aa f0 c4 dsti dsto f0o b1 7 b1 6 b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 b1 7 b1 6 b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 b1 7 b1 7 channel time 0 aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aaa a aaa a aaa a aaa aaaa a a a a a a aaaaa a a a a a a aaaaa a a a a a a a aaa a aaa a aaa a aaa a aaa aaaa a a a a a a aaaaa a a a a a a a aaaa aaaa a a a a a a a a a f0 c4 dsti dsto f0o b1 7 b1 6 b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 b1 7 b1 7 channel time 0 b1 7 b1 6 b1 5 b1 4 b1 3 b1 2 b1 1 b1 0 b2 7 b2 6 b2 5 b2 4 b2 3 b2 2 b2 1 b2 0 b2 7 b2 6 b2 5 b2 4 b2 3 b2 2 b2 1 b2 0 channel time 16
MT8971B/72b 9-110 functional description the MT8971B/72b is a device which has been designed primarily as an interface for the integrated services digital network (isdn). however, it may be used in practically any application that requires high speed data transmission over two wires, including smart telephone sets, workstations, data terminals and computers. in the isdn, the dnic is ideal for providing the interface at the u reference point. the device supports the 2b+d channel format (two 64 kbit/s b- channels and one 16 kbit/s d-channel) over two wires as recommended by the ccitt. the line data is converted to and from the st-bus format on the system side of the network to allow for easy interfacing with other components such as the s- interface device in an nt1 arrangement, or to digital pabx components. smart telephone sets with data and voice capability can be easily implemented using the MT8971B/72b as a line interface. the devices high bandwidth and long loop length capability allows its use in a wide variety of sets. this can be extended to provide full data and voice capability to the private subscriber by the installation of equipment in both the home and central office or remote concentration equipment. within the subscriber equipment the MT8971B/72b would terminate the line and encode/ decode the data and voice for transmission while additional electronics could provide interfaces for a standard telephone set and any number of data ports supporting standard data rates for such things as computer communications and telemetry for remote meter reading. digital workstations with a high degree of networking capability can be designed using the dnic for the line interface, offering up to 160 kbit/s data transmission over existing telephone lines. the MT8971B/72b could also be valuable within existing computer networks for connecting a large number of terminals to a computer or for intercomputer links. the highest data rates existing for terminal to computer links is 19.2 kbit/s over conventional analog modems. with the dnic, this can be increased up to 160 kbit/s at a very low cost per line for terminal to computer links and in many cases this bandwidth would be sufficient for computer to computer links. figure 1 shows the block diagram of the MT8971B/ 72b. the dnic provides a bidirectional interface between the dv (data/voice) port and a full duplex line operating at 80 or 160 kbit/s over a single pair of twisted wires. the dnic has three serial ports. the dv port (dsti/di, dsto/do), the cd (control/data) port (cdsti/cdi, cdsto/cdo) and a line port (l in , l out ). the data on the line is made up of information from the dv and cd ports. the dnic must combine information received from both the dv and cd ports and put it onto the line. at the same time, the data received from the line must be split into the various channels and directed to the proper ports. the usable data rates are 72 and 144 kbit/s as required for the basic rate interface in isdn. full duplex transmission is made possible through on board adaptive echo cancellation. the dnic has various modes of operation which are selected through the mode select pins ms0-2. the two major modes of operation are the modem (mod) and digital network (dn) modes. mod mode is a transparent 80 or 160 kbit/s modem. in dn mode the line carries the b and d channels formatted for the isdn at either 80 or 160 kbit/s. in the dn mode the dv and cd ports are standard st- bus and in mod mode they are transparent serial data streams at 80 or 160 kbit/s. other modes include: master (mas) or slave (slv) mode, where the timebase and frame synchronization are provided externally or are extracted from the line and dual or single (singl) port modes, where both the dv and cd ports are active or where the cd port is inactive and all information is passed through the dv port. for a detailed description of the modes see operating modes section. in digital network (dn) mode there are three channels transferred by the dv and cd ports. they are the b, c and d channels. the b1 and b2 channels each have a bandwidth of 64 kbit/s and are used for carrying pcm encoded voice or data. these channels are always transmitted and received through the dv port (figures 3, 4, 5, 6). the c- channel, having a bandwidth of 64 kbit/s, provides a means for the system to control the dnic and for the dnic to pass status information back to the system. the c-channel has a housekeeping (hk) bit which is the only bit of the c-channel transmitted and received on the line. the 2b+d channel bits and the hk bit are double-buffered. the d-channel can be transmitted or received on the line with either an 8, 16 or 64 kbit/s bandwidth depending on the dnics mode of operation. both the hk bit and the d- channel can be used for end-to-end signalling or low speed data transfer. in dual port mode the c and d channels are accessed via the cd port (figure 7) while in singl port mode they are transferred through the dv port (figures 5, 6) along with the b1 and b2 channels.
MT8971B/72b 9-111 figure 5 - dv port - 80 kbit/s (modes 0,4) figure 6 - dv port - 160 kbit/s (modes 0,4) aaaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa aaaa aa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa aaaa a aaa a aaa a aaa aaaa aa a a a a a a aa aaaa a aaa a aaa a aaa aaaa aa a a a a a a aa aaaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa aaaa aa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa channel time 0 d-channel channel time 1 c-channel channel time 2 b1-channel 11.7 m sec f0 c4 dsto dsti f0o d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 d 0 d 0 aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a a a a a a a a a a a a a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa a aaa aaaa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa a aaa a aaa a aaa a aaa aaaa a a a a a a a a aa aaaa aaaa aaaa aaaa aaaa a a a a a channel time 0 d-channel channel time 1 c-channel channel time 2 b1-channel 15.6 m sec f0 c4 dsto dsti f0o d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 d 0 d 0 channel time 3 b2-channel b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0
MT8971B/72b 9-112 in digital network (dn) mode, upon entering the dnic from the dv and cd ports, the b-channel data, d-channel d0 (and d1 for 160 kbit/s), the hk bit of the c-channel (160kbit/s only) and a sync bit are combined in a serial format to be sent out on the line by the transmit interface (figures 11, 12). the sync bit produces an alternating 1-0 pattern each frame in order for the remote end to extract the frame alignment from the line. it is possible for the remote end to lock on to a data bit pattern which simulates this alternating 1-0 pattern that is not the true sync. to decrease the probability of this happening the dnic may be programmed to put the data through a prescrambler that scrambles the data according to a predetermined polynomial with respect to the sync bit. this greatly decreases the probability that the sync pattern can be reproduced by any data on the line. in order for the echo canceller to function correctly, a dedicated scrambler is used with a scrambling algorithm which is different for the slv and mas modes. these algorithms are calculated in such a way as to provide orthogonality between the near and far end data streams such that the correlation between the two signals is very low. for any two dnics on a link, one must be in slv mode with the other in mas mode. the scrambled data is differentially encoded which serves to make the data on the line polarity-independent. it is then biphase encoded as shown in figure 10. see line interface section for more details on the encoding. before leaving the dnic the differentially encoded biphase data is passed through a pulse-shaping bandpass transmit filter that filters out the high and low frequency components and conditions the signal for transmission on the line. the composite transmit and receive signal is received at l in . on entering the dnic this signal passes through a precanceller which is a summing amplifier and lowpass filter that partially cancels the near-end signal and provides first order antialiasing for the received signal. internal, partial cancellation of the near end signal may be disabled by holding figure 7 - cd port (modes 2,6) figure 8 - cd port (modes 1,5) aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaaaaaaaa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa aa aa aaaaaaaaaaaaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaaaaaaaaa aa aa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aaa aaa aaa aaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaaaaaaaaaa aaaa a aaa a aaa a aaa a aaa aaaa a a a a a a aaaaa a a a a a a aaaaa a a a a a a aaaa a aaa a aaa a aaa a aaa a aaa aaaa a a a a a a a aaaa aaaa a a a a a a a a a aaaa aaaa a a a a a a a a a f0 c4 cdsto cdsti f0o c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 c 0 c 0 3.9 m sec 62.5 m sec 125 m sec channel time 0 channel time 16 cld tck cdi cdo c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 6 c 7 c 0 c 1 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 6 c 7 c 0 c 1
MT8971B/72b 9-113 the precan pin high. this mode simplifies the design of external line transceivers used for loop extension applications. the precan pin features an internal pull-down which allows this pin to be left unconnected in applications where this function is not required. the resultant signal passes through a receive filter to bandlimit and equalize it. at this point, the echo estimate from the echo canceller is subtracted from the precancelled received signal. this difference signal is then input to the echo canceller as an error signal and also squared up by a comparator and passed to the biphase receiver. within the echo canceller, the sign of this error signal is determined. depending on the sign, the echo estimate is either incremented or decremented and this new estimate is stored back in ram. the timebase in both slv and mas modes (generated internally in slv mode and externally in mas mode) is phase-locked to the received data stream. this phase-locked clock operates the biphase decoder, descrambler and deprescrambler in mas mode and the entire chip in slv mode. the biphase decoder decodes the received encoded bit stream resulting in the original nrz data which is passed onto the descrambler and deprescrambler where the data is restored to its original content by performing the reverse polynomials. the sync bits are extracted and the receive interface separates the channels and outputs them to the proper ports in the proper channel times. the destination of the various channels is the same as that received on the input dv and cd ports. the transmit/receive timing and control block generates all the clocks for the transmit and receive functions and controls the entire chip according to the control register. in order that more than one dnic may be connected to the same dv and cd ports an f0o signal is generated which signals the next device in a daisy chain that its channel times are now active. in this arrangement only the first dnic in the chain receives the system f0 with the following devices receiving its predecessors f0o . in mod mode, all the ports have a different format. the line port again operates at 80 or 160 kbit/s, however, there is no synchronization overhead, only transparent data. the dv and cd ports carry serial data at 80 or 160 kbit/s with the dv port transferring all the data for the line and the cd port carrying the c-channel only. in this mode the transfer of data at both ports is synchronized to the tck and rck clocks for transmit and receive data, respectively. the cld signal goes low to indicate the start of the c-channel data on the cd port. it is used to load and latch the input and output c-channel but has no relationship to the data on the dv port. operating modes (ms0-2) the logic levels present on the mode select pins ms0, ms1 and ms2 program the dnic for different operating modes and configure the dv and cd ports accordingly. table 1 shows the modes corresponding to the state of ms0-2. these pins select the dnic to operate as a master or slave, in dual or single port operation, in modem or digital network mode and the order of the c and d channels on the cd port. table 2 provides a description of each mode and table 3 gives a pin configuration according to the mode selected for all pins that have variable functions. these functions vary depending on whether it is in mas or slv, and whether dn or mod mode is used. the overall mode of operation of the dnic can be programmed to be either a baseband modem (mod mode) or a digital network transceiver (dn mode). as a baseband modem, transmit/receive data is passed transparently through the device at 80 or 160 kbit/s by the dv port. the cd port transfers the c-channel and d-channel also at 80 or 160 kbit/s. in dn mode, both the dv and cd ports operate as st-bus streams at 2.048 mbit/s. the dv port transfers data over pins dsti and dsto while on the table 1. mode select pins e=enabled x=not applicable blanks are disabled mode select pins mode operating mode ms2 ms1 ms0 slv mas dual singl mod dn d-c c-d ode 00 0 0 e e e e e 00 1 1 e e e x x e 01 0 2 e e e e e 01 1 3 e e e e e 10 0 4 e e e e e 10 1 5 e e e x x e 11 0 6 e e e e e 11 1 7 e e e e
MT8971B/72b 9-114 cd port, the cdsti and cdsto pins are used. the singl port option only exists in dn mode. in mod mode, dual port operation must be used and the d, b1 and b2 channel designations no longer exist. the selection of slv or mas will determine which of the dnics is using the externally supplied clock and which is phase locking to the data on the line. due to jitter and end to end delay, one end must be the master to generate all the timing for the link and the other must extract the timing from the receive data and synchronize itself to this timing in order to recover the synchronous data. dual port mode allows the user to use two separate serial busses: the dv port for pcm/data (b channels) and the cd port for control and signalling information (c and d channels). in the singl port mode, all four channels are concatenated into one serial stream and input to the dnic via the dv port. the order of the c and d channels may be changed only in dn/ dual mode. the dnic may be configured to transfer the d-channel in channel 0 and the c- channel in channel 16 or vice versa. one other feature exists; ode, where both the dv and cd ports are tristated in order that no devices are damaged due to excessive loading while all dnics are in a random state on power up in a daisy chain arrangement. table 2. mode definitions table 3. pin configurations mode function slv slave - the chip timebase is extracted from the received line data and the external 10.24 mhz crystal is phase locked to it to provide clocks for the entire device and are output for the external system to synchronize to. mas master - the timebase is derived from the externally supplied data clocks and 10.24 mhz clock which must be frequency locked. the transmit data is synchronized to the system timing with the receive data recovered by a clock extracted from the receive data and resynchronized to the system timing. dual dual port - both the cd and dv ports are active with the cd port transferring the c&d channels and the dv port transferring the b1& b2 channels. singl single port - the b1& b2, c and d channels are all transferred through the dv port. the cd port is disabled and cdsti should be pulled high. mod modem - baseband operation at 80 or 160 kbits/s. the line data is received and transmitted through the dv port at the baud rate selected. the c-channel is transferred through the cd port also at the baud rate and is synchronized to the cld output. dn digital network - intended for use in the digital network with the dv and cd ports operating at 2.048 mbits/s and the line at 80 or 160 kbits/s configured according to the applicable isdn recommendation. d-c d before c-channel - the d-channel is transferred before the c-channel following f0 . c-d c before d-channel - the c-channel is transferred before the d-channel following f0 . ode output data enable - when mode 7 is selected, the dv and cd ports are put in high impedance state. this is intended for power-up reset to avoid bus contention and possible damage to the device during the initial random state in a daisy chain configuration of dnics. in all the other modes of operation dv and cd ports are enabled during the appropriate channel times. mode # f0 /cld f0o /rck c4 /tck name input/output name input/output name input/output 0f0 input f0o output c4 input 1cld output rck output tck output 2f0 input f0o output c4 input 3f0 input f0o output c4 input 4f0 output f0o output c4 output 5cld output rck output tck output 6f0 output f0o output c4 output 7f0 input f0o output c4 input
MT8971B/72b 9-115 dv port (dsti/di, dsto/do) the dv port transfers data or pcm encoded voice to and from the line according to the particular mode selected by the mode select pins. the modes affecting the configuration of the dv port are mod or dn and dual or singl. in dn mode the dv port operates as an st-bus at 2.048 mbit/s with 32, 8 bit channels per frame as shown in figure 9. in this mode the dv port channel configuration depends upon whether dual or singl port is selected. when dual port mode is used, the c and d channels are passed through the cd port and the b1 and b2 channels are passed through the dv port. at 80 kbit/s only one channel of the available 32 at the dv port is utilized, this being channel 0 which carries the b1-channel. this is shown in figure 3. at 160 kbit/s, two channels are used, these being 0 and 16 carrying the b1 and b2 channels, respectively. this is shown in figure 4. when singl port mode is used, channels b1, b2, c and d are all passed via the dv port and the cd port is disabled. see cd port description for an explanation of the c and d channels. the d-channel is always passed during channel time 0 followed by the c and b1 channels in channel times 1 and 2, respectively for 80 kbit/s. see figure 5. for 160 kbit/s the b2 channel is added and occupies channel time 3 of the dv port. see figure 6. for all of the various configurations the bit orders are shown by the respective diagram. in mod mode the dv and cd ports no longer operate at 2.048 mbits/s but are continuous serial bit streams operating at the bit rate selected of 80 or 160 kbit/s. while in the mod mode only dual port operation can be used. in order for more than one dnic to be connected to any one dv and cd port, making more efficient use of the busses, the dsto and cdsto outputs are put into high impedance during the inactive channel times of the dnic. this allows additional dnics to be cascaded onto the same dv and cd ports. when used in this way a signal called f0o is used as an indication to the next dnic in a daisy chain that its channel time is now active. only the first dnic in the chain receives the system frame pulse and all others receive the f0o from its predecessor in the chain. this allows up to 16 dnics to be cascaded. cd port (cdsti/cdi, cdsto/cdo) the cd port is a serial bidirectional port used only in dual port mode. it is a means by which the dnic receives its control information for things such as setting the bit rate, enabling internal loopback tests, sending status information back to the system and transferring low speed signalling data to and from the line. the cd port is composed of the c and d-channels. the c-channel is used for transferring control and status information between the dnic and the system. the d-channel is used for sending and receiving signalling information and lower speed data between the line and the system. in dn/dual mode the dnic receives a c-channel on cdsti while transmitting a c-channel on cdsto. f ifteen channel times later (halfway through the frame) a d- channel is received on cdsti while a d-channel is transmitted on cdsto. this is shown in figure 7. the order of the c and d bytes in dual port mode can be reversed by the mode select pins. see table 1 for a listing of the byte orientations. the d-channel exists only in dn mode and may be used for transferring low speed data or signalling information over the line at 8, 16 or 64 kbit/s (by using the dinb feature). the information passes transparently through the dnic and is transmitted to or received from the line at the bit rate selected in the control register. if the bit rate is 80 kbit/s, only d0 is transmitted and received. at 160 kbit/s, d0 and d1 are transmitted and received. when the dinb bit is set in the control register the entire d-channel is transmitted and received in the b1-channel timeslot. figure 9 - st-bus format channel 0 channel 1 channel 2 ? ? ? ? ? ? ? ? bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 125 m sec channel 31 channel 30 channel 31 channel 0 channel 29 f0 st-bus most significant bit (first) least significant bit (last) 3.9 m sec
MT8971B/72b 9-116 the c-channel is used for transferring control and status information between the dnic and the system. the control and diagnostics registers are accessed through the c-channel. they contain information to control the dnic and carry out the diagnostics as well as the hk bit to be transmitted on the line as described in tables 4 and 5. bits 0 and 1 of the c-channel select between the control and diagnostics register. if these bits are 0, 0 then the c-channel information is written to the control register (table 4). if they are 0, 1 the c- c hannel is written to the diagnostics register (table 5). the diagnostics register reset bit (bit 2) of the control register determines the reset state of the diagnostics register. if, on writing to the control register, this bit is set to logic 0, the diagnostics register will be reset coincident with the frame pulse. when this bit is logic 1, the diagnostics register will not be reset. in order to use the diagnostic features, the diagnostics register must be continuously written to. the output c-channel sends status information from the status register to the system along with the received hk bit as shown in table 6. in mod mode, the cd port is no longer an st-bus but is a serial bit stream operating at the bit rate selected. it continues to transfer the c-channel but the d-channel and the hk bit no longer exist. dual port operation must be used in mod mode. the c- channel is clocked in and out of the cd port by tck table 4. control register notes: suggested use of attack: -at 160 kbit/s full convergence requires 850 ms with attack held high for the first 240 frames or 30 ms. -at 80 kbit/s full convergence requires 1.75 s with attack held high for the first 480 frames or 60 ms. when bits 4-7 of the control register are all set to one, the dnic operates in one of the default modes as defined in table 4a, depending upon the status of bit-3. bit name description 0 reg sel-1 register select-1. must be set to 0 to select the control register. 1 reg sel-2 register select-2. must be set to 0 to select the control register. 2 drr diagnostics register reset. writing a "0" to this bit will cause a diagnostics register reset to occur coincident with the next frame pulse as in the mt8972a. when this bit is a logic "1", the diagnostics register will not be reset. 3 brs bit rate select. when set to 0 selects 80 kbit/s. when set to 1, selects 160 kbit/s. 4dinb d-channel in b timeslot. when 0, the d-channel bits (d0 or d0 and d1) corresponding to the selected bit rate (80 or 160 kbit/s) are transmitted during the normal d-channel bit times. when set to 1, the entire d-channel (d0-d7) is transmitted during the b1-channel timeslot on the line providing a 64 kbit/s d-channel link. 5 psen prescrambler/deprescrambler enable. when set to 1, the data prescrambler and deprescrambler are enabled. when set to 0, the data prescrambler and deprescrambler are disabled. 6attack convergence speedup. when set to 1, the echo canceller will converge to the reflection coefficient much faster. used on power-up for fast convergence. when 0, the echo canceller will require the normal amount of time to converge to a reflection coefficient. 7 txhk transmit housekeeping. when set to 0, logic zero is transmitted over the line as housekeeping bit. when set to 1, logic one is transmitted over the line as housekeeping bit. bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 reg sel-1 reg sel-2 drr brs dinb psen attack txhk default mode selection (refer to table 4a)
MT8971B/72b 9-117 table 4a. default mode selection notes: a default mode 1 can also be selected by tying cdsti/cdi pin low when dnic is operating in dual mode. ? default mode 2 can also be selected by tying cdsti/cdi pin high when dnic is operating in dual mode. table 5. diagnostic register notes: when bits 4-7 of the diagnostic register are all set to one, the dnic operates in one of the default modes as defined in table 4a, depending upon the status of bit-3. do not use l out to l in loopback in dn/slv mode. a do not use dsto to dsti loopback in mod/mas mode. c-channel (bit 0-7) internal control register internal diagnostic register description xxx01111 00000000 01000000 default mode-1 a : bit rate is 80 kbit/s. attack, psen, dinb, drr and all diagnostics are disabled. txhk=0. xxx11111 00010000 01000000 default mode-2 ? bit rate is 160 kbit/s. attack, psen, dinb, drr and all diagnostics are disabled. txhk=0. bit name description 0 reg sel-1 register select-1. must be set to 0 to select the diagnostic register. 1 reg sel-2 register select-2. must be set to 1 to select the diagnostic register. 2,3 loopback bit 2 bit 3 0 0 all loopback testing functions disabled. normal operation. 0 1 dsti internally looped back into dsto for system diagnostics. 10l out is internally looped back into l in for system diagnostics. 1 1 dsto is internally looped back into dsti for end-to-end testing. a 4fun force unsync. when set to 1, the dnic is forced out-of-sync to test the sync recovery circuitry. when set to 0, the operation continues in synchronization. 5 pswap polynomial swap. when set to 1, the scrambling and descrambl ing polynomials are interchanged (use for mas mode only). when set to 0, the polynomials retain their normal designations. 6dlo disable line out. when set to 1, the signal on l out is set set to v bias . when set to 0, l out pin functions normally. 7 not used must be set to 0 for normal operation. bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 reg sel-1 reg sel-2 loopback fun pswap dlo not used default mode selection (refer to table 4a) and cld with tck defining the bits and cld the channel boundaries of the data stream as shown in figure 8. line port (l in , l out ) the line interface is made up of l out and l in with l out driving the transmit signal onto the line and l in receiving the composite transmit and receive signal from the line. the line code used in the dnic is biphase and is shown in figure 10. the scrambled nrz data is differentially encoded meaning the previous differential encoded output is xord with the current data bit which produces the current output. this is then biphase encoded where transitions occur midway through the bit cell with a negative going transition indicating a logic "0" and a positive going transition indicating a logic "1".
MT8971B/72b 9-118 table 6. status register status register name function 0 sync synchronization - when set this bit indicates that synchronization to the received line data sync pattern has been acquired. for dn mode only. 1-2 chqual channel quality - these bits provide an estimate of the receivers margin against noise. the farther this 2 bit value is from 0 the better the snr. 3 rx hk housekeeping - this bit is the received housekeeping (hk) bit from the far end. 4-6 future future functionality. these bits return logic 1 when read. 7 id this bit provides a hardware identifier for the dnic revision. the mt8972b will return a logic 0 for this bit. (logic 1 returned for mt8972a.) 01234567 sync chqual rx hk future functiona lity id there are some major reasons for using a biphase line code. the power density is concentrated in a spectral region that minimizes dispersion and differential attenuation. this can shorten the line response and reduce the intersymbol interference which are critical for adaptive echo cancellation. there are regular zero crossings halfway through every bit cell or baud which allows simple clock extraction at the receiving end. there is no d.c. content in the code so that phantom power feed may be applied to the line and simple transformer coupling may be used with no effect on the data. it is bipolar, making data reception simple and providing a high signal to noise ratio. the signal is then passed through a bandpass filter which conditions the signal for the line by limiting the spectral content from 0.2f baud to 1.6f baud and on to a line driver where it is made available to be put onto the line biased at v bias . the resulting transmit signal will have a distributed spectrum with a peak at 3/4f baud . the transmit signal (l out ) may be disabled by holding the l out dis pin high or by writing dlo (bit 6) of the diagnostics register to logic 1. when disabled, l out is forced to the v bias level. l out dis has an internal pull-down to allow this pin to be left not connected in applications where this function is not required. the receive signal is the above transmit signal superimposed on the signal from the remote end and any reflections or delayed symbols of the near end signal. the frame format of the transmit data on the line is shown in figures 11 and 12 for the dn mode at 80 and 160 kbit/s. at 80 kbit/s a sync bit for frame recovery, one bit of the d-channel and the b1- channel are transmitted. at 160 kbit/s a sync bit, the hk bit, two bits of the d-channel and both b1 and b2 channels are transmitted. if the dinb bit of the control register is set, the entire d-channel is transmitted during the b1- channel timeslot. in mod mode the sync, hk and d-channel bits are not transmitted or received but rather a continuous data stream at 80 or 160 kbit/s is present. no frame recovery information is present on the line in mod mode.
MT8971B/72b 9-119 figure 10 - data & line encoding figure 11 - frame format - 80 kbit/s (modes 0, 2, 3, 4, 6) figure 12 - frame format - 160 kbit/s (modes 0, 2, 3, 4, 6) a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a bits data nrz data differential encoded differential encoded biphase transmit line signal bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 11100100 v bias note: last bit sent was a logic 0 f0 l out b1 7 sync d 0 b1 0 b1 1 b1 2 b1 3 b1 4 b1 5 b1 6 b1 7 sync f0 l out sync hk0 d 1 d 0 b1 0 b1 1 b1 2 b1 3 b1 4 b1 5 b1 6 b1 7 b2 0 b2 1 b2 2 b2 3 b2 4 b2 5 b2 6 b2 7 sync
MT8971B/72b 9-120 applications typical connection diagrams are shown in figures 13 and 14 for the dn mode as a master and slave, respectively. l out is connected to the coupling transformer through a resistor r2 and capacitors c2 and c2 to match the line characteristic impedance. suggested values of r2, c2 and c2 for 80 and 160 kbit/s operation are provided in figures 13 and 14. overvoltage protection is provided by r1, d1 and d2. c1 is present to properly bias the received line signal for the l in input. a 2:1 coupling transformer is used to couple to the line with a secondary center tap for optional phantom power feed. varistors have been shown for surge protection against such things as lightning strikes. if the scramblers power up with all zeros in them, they are not capable of randomizing all-zeros data sequence. this increases the correlation between the transmit and receive data which may cause loss of convergence in the echo canceller and high bit error rates. in dn mode the insertion of the sync pattern will provide enough pseudo-random activity to maintain convergence. in mod mode the sync pattern is not inserted. for this reason, at least one 1 must be fed into the dnic on power up to ensure that the scramblers will randomize any subsequent all-zeros sequence. figure 13 - typical connection diagram - mas/dn mode, 160 kbit/s figure 14 - typical connection diagram - slv/dn mode, 160 kbit/s dv port st-bus cd port st-bus master clocks mode select lines { { { +5v 0.33 m f 0.33 m f dsti dsto cdsti cdsto f0 c4 ms0 ms1 ms2 v ref v bias l out l in osc1 osc2 f0o nc d.c. coupled, frequency locked 10.24 mhz clock. r2 = 390 w r1 = 47 w c2 = 1.5 nf c2 = 22 nf +5v d1 = d2 = mur405 d2 2 : 1 1.0 m f line feed voltage for 80 kbit/s: c2 = 3.3 nf c1 = 0.33 m f 68 volts (typ) 2.5 joules 0.02 watt note: low leakage diodes (1 & 2) are required so that the dc voltage at l in ? v bias to next dnic MT8971B/72b refer to ac electrical characteristics dn mode clock timing dv port st-bus cd port st-bus master clocks mode select lines +5v 0.33 m f 0.33 m f dsti dsto cdsti cdsto f0 c4 ms0 ms1 ms2 v ref v bias l out l in osc1 osc2 r2 = 390 w r1 = 47 w c2 = 1.5 nf c2 = 22 nf +5v d1 = d2 = mur405 d2 2:1 { { { 1.0 m f for 80 kbit/s: c2 = 3.3 nf c1 = 0.33 m f 68 volts (typ) 0.02 watt note: low leakage diodes (1 & 2) are required so 2.5 joules that the dc voltage at l in ? v bias 10.24 mhz xtal c3=33pf=c4 supply MT8971B/72b
MT8971B/72b 9-121 ** exceeding these values may cause permanent damage. functional operation under these conditions is not implied. * typical figures are at 25c and are for design aid only: not guaranteed and not subject to production testing. ? parameters over recommended temperature & power supply voltage ranges. * typical figures are at 25c and are for design aid only: not guaranteed and not subject to production testing. ? parameters over recommended temperature & power supply voltage ranges. absolute maximum ratings ** - voltages are with respect to ground (v ss ) unless otherwise stated. parameter symbol min max units 1 supply voltage v dd -0.3 7 v 2 voltage on any pin (other than supply) v max -0.3 v dd +0.3 v 3 current on any pin (other than supply) i max 40 ma 4 storage temperature t st -65 +150 c 5 package power dissipation (derate 16mw/c above 75c) p diss 750 mw recommended operating conditions ? - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ* max units test conditions 1 operating supply voltage v dd 4.75 5.00 5.25 v 2 operating temperature t op -40 +85 c 3 input high voltage (except osc1) v ih 2.4 v dd v for 400 mv noise margin 4 input low voltage (except osc1) v il 0 0.4 v for 400 mv noise margin dc electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ* max units test conditions 1 o u t p u t s operating supply current i dd 10 15 ma 2 output high voltage (ex osc2) v oh 2.4 v i oh =10ma 3 output high current (except osc2) output high current - osc2 i oh 10 15 ma source current. v oh =2.4v 4 8 12 ma source current. v oh =3.0v 5i oh 10 a source current v oh =3.5v 6 output low voltage (ex osc2) v ol 0.4 v i ol =5ma 7 output low current (except osc2) output low current - osc2 i ol 5 7.5 ma sink current. v ol =0.4v 8 20 30 ma sink current. v ol =2.0v 9i ol 10 a sink current. v ol =1.5v 10 high imped. output leakage i oz 10 av in =v ss to v dd 11 output voltage (v ref ) (v bias ) v o v bias - 1.8 v dd /2 v v 12 13 i n p u t s input high voltage (ex osc1) v ih 2.0 v 14 input low voltage (ex osc1) v il 0.8 v 15 input high voltage (osc1) v iho 4.0 v 16 input low voltage (osc1) v ilo 1.0 v 17 input leakage current i il 10 av in =v ss to v dd 18 input pulldown impedance l out dis and precan z pd 50 k w 19 input leakage current for osc1 input i iosc 20 40 a
MT8971B/72b 9-122 ? timing is over recommended temperature & power supply voltages. * typical figures are at 25c and are for design aid only: not guaranteed and not subject to production testing. duty cycle is measured at v dd /2 volts. . ? timing is over recommended temperature & power supply voltages. * typical figures are at 25c and are for design aid only: not guaranteed and not subject to production testing. notes: 1) when operating as a slave the c4 clock has a 40% duty cycle. 2) when operating in mas/dn mode, the c4 and oscillator clocks must be externally frequency-locked (i.e., f c =2.5xf c4 ). the relative phase between these two clocks ( f in fig. 17) is not critical and may vary from 0 ns to t c4p . however, the relative jitter must be less than j c (see figure 17). figure 15 - c4 clock & frame pulse alignment for st-bus streams ac electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ* max units test conditions 1 i n p u t s input voltage (l in) v in 5.0 v pp 2 input current (l in )i in -10 +10 af baud =160 khz 3 input impedance (l in )z in 20 40 k w f baud =160 khz 4 crystal/clock frequency f c 10.24 mhz 5 crystal/clock tolerance t c -100 0 +100 ppm 6a crystal/clock duty cycle dc c 40 50 60 % normal temp. & v dd 6b crystal/clock duty cycle dc c 45 50 55 % recommended at max./ min. temp. & v dd 7 crystal/clock loading c l 33 50 pf from osc1 & osc2 to v ss . 8 o u t p u t s output capacitance (l out )c o 8pf 9 load resistance (l out ) (v bias , v ref ) r lout 500 100 w k w 10 load capacitance (l out ) (v bias , v ref ) c lout 0.1 20 pf f capacitance to v bias . 11 output voltage (l out )v o 3.2 4.3 4.6 v pp r lout = 500 w , c lout = 20pf ac electrical characteristics ? - clock timing - dn mode (figures 16 & 17) characteristics sym min typ* max units test conditions 1c4 clock period t c4p 244 ns 2c4 clock width high or low t c4w 90 122 150 ns in master mode - note 1 3 frame pulse setup time t f0s 50 ns 4 frame pulse hold time t f0h 50 ns 5 frame pulse width t f0w 172 244 ns 6 10.24 mhz clock jitter (wrt c4 )j c -15 +15 ns note 2 channel 31 bit 0 channel 0 bit 7 channel 0 bit 6 f0b c4 st-bus bit cells
MT8971B/72b 9-123 figure 16 - c4 clock & frame pulse alignment for st-bus streams in dn mode figure 17 - frequency locking for the c4 and osc1 clocks in mas/dn mode ? timing is over recommended temperature & power supply voltage ranges. * typical figures are at 25c, for design aid only: not guaranteed and not subject to production testing. figure 18 - rck , tck & cld timing for mod mode ac electrical characteristics ? - clock timing - mod mode (figure 18) characteristics sym 80 kbit/s 160 kbit/s units test conditions min typ* max min typ* max 1tck /rck clock period t cp 12.5 6.25 s 2 tck /rck clock width t cw 6.25 3.125 s 3 tck /rck clock transition time t ct 20 20 ns c l =40pf 4cld to tck setup time t clds 3.125 1.56 s 5cld to tck hold time t cldh 3.125 1.56 s 6cld width low t cldw 6.05 2.925 s 7cld period t cldp 8 x t cp 8 x t cp s c4 f0 2.0v 0.8v 2.0v 0.8v t c4p t c4w t f0s t f0h t f0w t c4w c4 osc1 2.0v 0.8v 3.0v 2.0v j c f rck tck cld t ct t cp t clds t cldh t cw t ct t cldw t cw 2.4v 0.4v 2.4v 0.4v 2.4v 0.4v t cp note 1: tck and cld are generated on chip and provide the data clocks for the cd port and the transmit section of the dv port. rck , also generated on chip, is extracted from the receive data and only clocks out the data at the d o output and may be skewed with respect to tck due to end-to-end delay. note 2: at the slave end tck is phase locked to rck . the rising edge of tck will lead the rising edge of rck by approximately 90 o .
MT8971B/72b 9-124 ? timing is over recommended temperature & power supply voltage ranges. * typical figures are at 25c, for design aid only: not guaranteed and not subject to production testing. figure 19 - data timing for dn mode ? timing is over recommended temperature & power supply voltage ranges. * typical figures are at 25c, for design aid only: not guaranteed and not subject to production testing. note 1 : attenuation measured from master l out to slave l in at 3/4baud frequency. * typical figures are at 25c, for design aid only: not guaranteed and not subject to production testing. ac electrical characteristics ? - data timing - dn mode (figure 19) characteristics sym min typ* max units test conditions 1 dsti/cdsti data setup time t rs 30 ns 2 dsti/cdsti data hold time t rh 50 ns 3a dsto/cdsto data delay t td 120 ns c l =40pf 3b dsto/cdsto high z to data delay t ztd 100 140 ns c l =40pf ac electrical characteristics ? - data timing - mod mode (figure 20) characteristics sym 80 kbit/s 160 kbit/s units test conditions min typ* max min typ* max 1 di/cdi data setup time t ds 150 150 ns 2 di/cdi data hold time t dh 4.5 2.5 s 3 do data delay time t rd 100 100 ns c l =40pf 4 cdo data delay time t td 100 100 ns c l =40pf performance characteristics of the MT8971B dsic characteristics sym min typ* max units test conditions 1 allowable attenuation for bit error rate of 10 -6 (note 1) a fb 03025 dbsnr 3 16.5db (300khz bandlimited noise) 2 line length at 80 kbit/s -24 awg -26 awg l 80 3.0 2.2 km attenuation - 6.9 db/km attenuation - 10.0 db/km 3 line length at 160 kbit/s -24 awg -26 awg l 160 3.0 2.2 km attenuation - 8.0 db/km attenuation - 11.5 db/km performance characteristics of the mt8972b dnic characteristics sym min typ* max units test conditions 1 allowable attenuation for bit error rate of 10 -6 (note 1) a fb 04033 dbsnr 3 16.5db (300khz bandlimited noise) 2 line length at 80 kbit/s -24 awg -26 awg l 80 5.0 3.4 km attenuation - 6.9 db/km attenuation - 10.0 db/km 3 line length at 160 kbit/s -24 awg -26 awg l 160 4.0 3.0 km attenuation - 8.0 db/km attenuation - 11.5 db/km 2.0v 0.8v 2.4v 0.4v 2.0v 0.8v bit stream c4 dsti cdsti dsto cdsto bit cell t td t rs t rh t td t ztd
MT8971B/72b 9-125 figure 20 - data timing for master modem mode tx bit stream tck di cdi cdo rx bit stream do 2.4v 0.4v 2.0v 0.8v 2.4v 0.4v 2.4v 0.4v bit cell t ds t dh t td t td t rd t rd bit cell rck
MT8971B/72b 9-126 figure 21 - data timing for slave modem mode tck di cdi cdo do 2.4v 0.4v 2.0v 0.8v 2.4v 0.4v 2.4v 0.4v t ds t dh t td t td rck ? t cp

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